1. Field of the Invention
The embodiments of the invention generally relate to circuit limited yield loss and, more specifically, to a system and an associated method for correcting systematic parametric variations on integrated circuit chips in order to minimize circuit limited yield loss.
2. Description of the Related Art
Circuit limited yield loss refers to the percentage of integrated circuit chips that, when manufactured according to a given design, will not/do not meet pre-defined performance expectations (e.g., clock frequency and power consumption expectations). Across-chip parametric variations (i.e., across-chip variations in device parameters such as threshold voltage, effective channel length, sheet resistance, drive current, leakage current, etc.) can cause significant variations in device performance and, thereby can cause circuit limited yield loss. Some across-chip parametric variations may be random. That is, they may be unpredictable. However, other across-chip parametric variations may be systematic (i.e., deterministic, predictable, etc.). For example, they may be process-based (i.e., the result of known limits on processing and/or processing controls). Alternatively, they may be design-based (i.e., the result of known design configurations). Typical solutions for systematic parametric variations include process and/or design changes. However, development and implementation of such solutions particularly with respect to design changes are often costly and time consuming. Therefore, it would be advantageous to provide a system and an associated method for correcting systematic parametric variations on integrated circuit chips during manufacture in order to minimize circuit limited yield loss without incurring significant cost and time penalties.